Wojciech Dabrowski writes the code nobody sees — and everybody depends on. A profile of an embedded engineer who measures success in microamps, microseconds and zero field returns.
Somewhere between the schematic and the finished product sits a layer of software that has to be perfect on the first try — because once a device is sealed, potted or shipped to a wind farm in the North Sea, there is no "quick fix". That layer is where Wojciech Dabrowski does his best work.
An Embedded Systems Developer based in Gniezno, Poland, he has spent the past decade writing firmware for microcontrollers that run industrial sensors, automotive modules and battery-powered medical wearables. His days are split between an IDE, a logic analyser and a well-worn oscilloscope.
"If it can't survive a brown-out, it isn't finished."
He is known for bringing up new hardware fast: reading the errata before the datasheet, getting a clock tree and a debug UART alive on day one, and building the drivers, RTOS tasks and test harnesses that turn a prototype into a product.
Colleagues describe him as the person you call when a bug only appears at −20 °C, once a week, on one board out of a hundred. He prefers deterministic code, honest timing budgets, static analysis over guesswork, and documentation the next engineer will actually read.
Off the clock he tinkers with open-source RISC-V boards and mentors students entering the field — insisting, every time, that they learn to read a scope trace before they learn to read a framework.
What's on the bench, in the editor and in the head. Rated by the subject himself — and verified by a decade of shipped hardware.
MISRA-C compliant drivers, modern C++17 on bare metal, zero-heap designs, linker scripts and startup code written by hand.
FreeRTOS, Zephyr and bare-metal superloops; task design, priority inversion hunting, rate-monotonic timing analysis.
ARM Cortex-M0+/M4/M7 (STM32, nRF52/53, NXP i.MX RT), ESP32 and RISC-V. Clock trees, DMA, low-power modes.
CAN / CAN-FD, SPI, I²C, UART, USB CDC, Modbus RTU, BLE GATT, LoRaWAN and MQTT for the connected edge.
Schematic review, oscilloscope and logic-analyser debugging, JTAG/SWD, power profiling down to nanoamps.
Unit tests with Unity/Ceedling, HIL rigs, static analysis, CMake, GitLab CI, secure boot and OTA update pipelines.
Four projects, four very different constraints. Every one of them is still running.
Battery-powered vibration and temperature node for predictive maintenance on pumps and motors. Custom tickless scheduler on an nRF52, event-driven sampling and LoRaWAN uplink — engineered to run on a single lithium cell for seven years.
Field-oriented control firmware for a BLDC motor driver in electric-bike drivetrains. Hand-tuned ISR budget, fixed-point math on a Cortex-M4F, sensorless startup and a fault-handling state machine that shuts down safely in under 5 µs.
Dual CAN-FD to Ethernet gateway for agricultural vehicles. Message filtering and routing in FreeRTOS with deterministic latency, J1939 diagnostics and a remote logging feature used to diagnose field issues without a technician on site.
A secure dual-bank bootloader and OTA update pipeline for a Class II wearable patient monitor. Signed images, anti-rollback counters and power-fail-safe swap logic, developed and documented to IEC 62304.
A career, collected. Every edition sold out.
Board that won't boot? A battery that dies in a week? A product that needs firmware done properly?
The editor reads every letter. Send a note about a full-time role, a contract, or a tricky bring-up — replies usually within one business day.